1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method of forming an isolation structure in a semiconductor substrate that reduces the chance of the isolation structure becoming recessed below the surface of the substrate.
2. Description of the Related Art
The fabrication of an integrated circuit involves the formation of numerous devices within active areas of a semiconductor substrate. Isolation structures are needed to electrically isolate one device from another. Isolation structures define the field regions of the semiconductor substrate, and the device areas define the active regions. The devices may be interconnected with conductive lines running over the isolation structures.
A popular isolation technology used in the fabrication of integrated circuits involves locally oxidizing silicon. In local oxidation of silicon ("LOCOS") processes, an oxide layer is first grown upon a silicon substrate. A silicon nitride ("nitride") layer is deposited upon the oxide layer. The oxide layer serves as a pad layer for the nitride layer. The surface of a field region of the silicon substrate is then exposed by etching portions of the nitride layer and oxide layer above this region. Active regions of the silicon substrate remain covered by the nitride layer, which is used as a mask to prevent oxidation of these regions in subsequent steps. A dopant implant is performed in the field region to create a channel-stop doping layer. The exposed portion of the silicon substrate within the field region is then oxidized. The silicon dioxide ("oxide") grown in the field region is termed field oxide. By growing a thick field oxide in isolation (or field) regions pre-implanted with a channel-stop dopant, LOCOS processing can help to prevent the establishment of parasitic channels in the field regions.
Although LOCOS has remained a popular isolation technology, the basic LOCOS process described above has several problems. When growing the field oxide, oxide growth should ideally be contained within the field region. In reality, however, some oxide growth may occur in a lateral direction, causing the field oxide to grow under and lift the edges of the nitride layer. Because the shape of the field oxide at the nitride edges is that of a slowly tapering wedge that merges into the pad oxide, the wedge is often described a bird's beak. In many instances, formation of the bird's beak can cause unacceptable encroachment of the field oxide into the active regions. In addition, the high temperatures associated with field oxide growth often cause the pre-implanted channel-stop dopant to migrate towards adjacent active regions. An increase in the dopant concentration near the edges of the field oxide can create a reduction in the drain current, an outcome that is often described as the narrow-width effect. Furthermore, thermal oxide growth is significantly less in small field regions (i.e., field areas of narrow lateral dimension) than in large field regions. Because of this reduction in oxide growth, an undesirable phenomenon known as the field-oxide-thinning effect may occur in small field regions. Field-oxide-thinning can produce problems with respect to field threshold voltages, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Despite advances made to decrease the bird's beak, channel-stop encroachment and non-planarity problems, it appears that LOCOS technology is still inadequate for deep submicron technologies. Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as trench isolation. Trench isolation methods are primarily characterized by the depth at which the trenches are formed: either shallow (&lt;1 micron), moderate (1-3 microns), or deep (&gt;3 microns). Of these, shallow trench isolation ("STI") is particularly popular in integrated circuit fabrication processes.
An isolation structure formed by a conventional shallow trench isolation process (hereinafter "the conventional STI process") is shown in FIG. 1. Silicon substrate 100 is a lightly doped wafer of single crystal silicon. The conventional STI process includes an initial step in which a relatively shallow trench (e.g., between 0.3 and 0.5 microns in depth) is etched in silicon substrate 100. The trench is then filled with trench dielectric 102, which is usually a deposited oxide. Some trench processes also include an intermediate step of growing an oxide liner on the trench floor and sidewalls before filling the trench with trench dielectric 102. After the trench is filled, the upper surface of trench dielectric 102 is then made coplanar with the upper surface of silicon substrate 100 to complete the isolation structure. In further processing, an interlevel dielectric layer 110 is typically deposited over the planarized surface. Conductive pattern 108 may be deposited and patterned over dielectric layer 110. Conductive pattern 108 includes metal lines used as global interconnection between devices, or alternatively, doped polysilicon used either as localized interconnect or as gate conductors of transistor gates.
The conventional STI process eliminates many of the problems of LOCOS techniques, including bird's beak and channel-stop dopant redistribution. STI processes are also better suited than LOCOS processes for isolating densely spaced active devices having field regions less than one micron wide. In addition, the trench isolation structure formed in STI processes is fully recessed, offering at least the potential for a planar surface. Moreover, field-oxide thinning in narrow isolation spaces is less likely to occur when using the shallow trench process. But despite its many advantages over LOCOS techniques, the conventional trench isolation process described above nevertheless has its own set of drawbacks.
One drawback of the conventional STI process results from the formation of sharp upper corners 106 where the sidewalls of trench 102 intersect with the surface of semiconductor substrate 100. Sharp upper corners 106 are typically a result of the highly directional etch used to form the trench. Sharp upper corners 106 may introduce certain undesirable effects during subsequent processing steps that can influence an integrated circuit's operation.
For instance, sharp upper comers 106 tend to congregate the electric fields in dielectric layer 110, which causes bunching of electric fields in the comer area. Because of this bunching of the electric field, the corner has a lower threshold voltage (V.sub.T) than the planar surfaces adjacent the trench corner. Consequently, the performance of a transistor formed in an adjacent active area is less than optimal since the transistor will experience a threshold gradient from the center of the channel to the edge of the channel where the electric fields are bunched.
The conventional STI process also includes a step in which trench dielectric 102 is planarized (this step is done before the formation of dielectric layer 110). After the planarization step, the upper surface of the trench dielectric is somewhat coplanar with the upper surface of semiconductor substrate 100. Subsequent processing steps, however, may lead to the upper surface of trench dielectric 102 being displaced significantly below the surface of semiconductor substrate 100. This is due, in part, to the removal of the nitride masking layer which, during removal, etches away a portion of the trench dielectric 102 laterally adjacent to the masking layer. Further, various cleaning procedures alone will attack and remove the trench dielectric.
For example, chemical-mechanical polishing ("CMP") is often used to planarize the trench dielectric. CMP is usually described as a "dirty" procedure because of the polishing-slurry particles and other residues that accumulate upon the surface of the semiconductor topography during the process. These contaminants must be cleaned from the semiconductor topography after the CMP process is complete. The RCA cleaning method commonly used to clean such contaminants also removes the upper surface of the trench dielectric to a slightly greater degree than the adjacent silicon within semiconductor substrate 100. In addition, steps that involve the etching of oxide layers may result in the recession of the upper surface of trench dielectric 102 below the upper surface of semiconductor substrate 100. Examples of such steps include stripping the sacrificial oxide layer commonly grown upon the silicon substrate before deposition of the gate oxide and etching an oxide layer deposited over a gate electrode to form sidewall spacers.
One problem caused by recession of the upper surface of trench dielectric 102 below the surface of silicon substrate 100 is further reduction of the isolation voltage at sharp upper corners 106. This reduction is believed to be caused by the increased electric field bunching that can result from recession of the trench dielectric upper surface. The increase in electric field bunching caused by recession of trench dielectric 102 below the surface of silicon substrate 100 can cause dielectric layer 110 to unexpectedly breakdown during operation of the circuit.
In addition to the issues discussed above, recession of the upper surface of trench dielectric 102 below the surface of semiconductor substrate 100 may also cause problems during silicide formation. After dopants have been implanted into source/drain junctions of the active regions between the gate conductor and adjacent trench dielectric structures, highly conductive ohmic contacts must be formed between the source/drain junctions and overlying interconnect. A self-aligned silicide ("salicide") is typically formed at the juncture between the ohmic contacts and the junctions. Salicide formation involves deposition of a refractory metal across the semiconductor topography followed by heating the refractory metal such that the metal reacts with the underlying silicon. Thus, a highly conductive silicide is formed upon the junctions.
If a trench dielectric is recessed below adjacent source/drain junctions such that sidewalls of the silicon substrate are exposed, silicide formation will occur upon those exposed sidewalls. Unfortunately, the relatively low resistivity silicide can form a conductive pathway between the source/drain junctions and the oppositely-doped underlying silicon substrate or well region. The presence of the conductive pathway may cause majority charge carriers to be drawn away from rather than toward the channel region of the transistor during operation. This shorting of the source-to-drain current flow can lead to inoperability of the transistor.
Therefore, it would be desirable to design a method for fabricating an isolation structure that reduced the chance of the isolation structure becoming recessed below the surface of the semiconductor substrate in which it was formed.